IEEE-iSES

DFT implementation at RTL stage: Methodology to enhance SoC Testability and reduce Time-to-Market

Abstract: In the VLSI design industry, Design-for-Testability (DFT) is still predominantly implemented during the gate-level stage in most projects. The DFT design cycle hasn’t changed much over the years with DFT hardware insertion at gate-level, followed by synthesis, test-pattern generation and simulation. This conventional method requires engineers to complete multiple design steps before any DRCs are detected, later in the development cycle. When such errors arise, the entire flow must be re-executed, resulting in delays in the overall design schedule.

The increasing complexity of modern integrated circuits demands the implementation of DFT at higher abstraction levels within the IC development cycle. Extensive research and publications already support the feasibility of implementing DFT at the RTL stage. Major EDA vendors have developed comprehensive tool flows to enable and streamline this approach. The DFT hardware implementation i.e., IJTAG, BScan, MBIST, OCC, Compression, LBIST, Wrappers and Test Point Insertion at RTL stage allow us to validate hardware at early stage of development cycle. In this tutorial, we will demonstrate how early-stage DFT planning can reduce test development time, improve test quality, and address challenges such as test vector volume and power optimization.

Jatin Chakravarti

Senior DFT engineer, eInfochips, India

Chintan Panchal

Fellow, eInfochips, India

Model-Based Hardware-Software Co-Synthesis of Embedded Systems

Abstract: Embedded systems for reactive real-time applications are typically implemented as hybrid hardware-software systems, based on microcontrollers/microprocessors, digital signal processors, and specialized hardware accelerator blocks. Software is used to impart flexibility and implement different features, while hardware is used to meet stringent performance requirements. Many different types of constraints, such as performance, power, robustness & reliability, weight, and cost, are major driving factors in the design and implementation of embedded systems.

While some effort is currently being carried out in various academic research communities to formalize the design process of embedded systems, much of the design, implementation, and verification in the industrial context is driven by ad-hoc approaches, where the overall embedded system specification is often captured in natural language, rendering it ambiguous and, many times, incomplete. This can lead to several problems, such as sub-optimal design, difficulty in re-design due to any specification revision, and an expensive verification effort.

In the tutorial, we highlight the need to adopt a methodology based on formal specification, automatic synthesis, and validation of embedded systems by carrying out the design in a unified framework supporting a unified hardware-software representation, which is unbiased to either hardware or software implementation. As an example, we show how formal approaches can help ease the specification, synthesis, verification & validation of applications running on such embedded systems. The tutorial aims to provide an understanding of System Level Design approaches using system abstractions and modeling through the use of System Level Design Languages and System Level Design automation tools to result in the implementation of functionally correct and cost-optimal complex Embedded Systems.

Prof. Subir Kumar Roy

IIIT Bangalore

Prof. Kusum Lata

LNMIIT Jaipur

Secure and high-performance designs/Architectures

Abstract: This tutorial provides a comprehensive overview of the challenge in designing modern computing systems to be simultaneously high-performance (low latency, high throughput) and secure (confidentiality, integrity, availability). The fundamental conflict, known as the Performance-Security Trade-Off, arises because traditional security measures, such as encryption and integrity checks, inevitably introduce significant overhead in terms of latency, power consumption, and area. We begin by defining the demands of High-Performance Computing (HPC)—which relies on massive parallelism, heterogeneous resources (CPUs, GPUs), and ultra-fast interconnects—and contrast them with the critical requirements of system security (the CIA Triad).

The necessity for specialized secure architectures is driven by the unique and expanded attack surface presented by large-scale HPC systems. These systems are vulnerable not just at the software layer, but also at the hardware level, facing threats like Side-Channel Attacks (SCA)— where timing or power consumption leak sensitive data (e.g., Spectre/Meltdown)—and risks within the supply chain, such as hardware Trojans. Furthermore, the sheer scale introduces challenges in maintaining data integrity and confidentiality for petabyte-scale parallel storage and high-speed data transmission over interconnects, where performance often dictates the disabling of traditional security features.

The core of the tutorial focuses on Co-Design Solutions that architecturally embed security to minimize performance impact. Key among these are Hardware-Assisted Security (HwAS) mechanisms like Trusted Execution Environments (TEE), such as Intel SGX and ARM TrustZone. These create isolated enclaves to protect code and data from compromised operating systems or hypervisors, offering strong security guarantees while striving to manage associated performance costs. A high-performance strategy involves using dedicated hardware accelerators like SmartNICs or DPUs (Data Processing Units) to offload security tasks (like encryption and intrusion detection) from the main CPUs, thereby preserving the computational throughput for the primary application workload.

Looking toward the future, the tutorial explores advanced topics essential for modern deployments including securing multi-tenant Cloud HPC environments using Zero Trust models and fine-grained Micro-segmentation. We also discuss the increasingly vital role of Artificial Intelligence and Machine Learning in system security, where AI is used to power real-time Intrusion Detection Systems (IDS) by analyzing system logs and performance telemetry for subtle anomalies that could signify an attack or a security breach. Finally, we address the challenge of future-proofing systems against emerging threats, specifically the architectural implications and performance burdens of supporting computationally intensive Post-Quantum Cryptography (PQC) algorithms.

Prof. Virendra Singh

Indian Institute of Technology Bombay (IITB), India

Demystifying Static Timing Analysis: From Fundamentals to Advanced Practices

Abstract: Static Timing Analysis (STA) is a cornerstone of modern digital VLSI design, ensuring that chips meet performance and reliability requirements before fabrication. This tutorial, delivered by Prof. Sneh Saurabh (IIIT Delhi), aims to demystify STA by bridging fundamental principles with advanced industry practices. The session begins with an intuitive exploration of timing concepts—setup, hold, clock skew, jitter, and timing windows—followed by a practical walkthrough of timing paths, constraints, and delay modeling. Participants will learn how STA tools analyze large-scale designs without requiring simulation, and how timing reports are interpreted for closure. The tutorial will further highlight real-world challenges such as multi-clock domains, PVT variations, false paths, multi-cycle paths, and optimization strategies. This comprehensive session is designed to benefit students, researchers, and engineers seeking a strong conceptual and practical grasp of STA.

Prof. Sneh Saurabh

Indraprastha Institute of Information Technology, Delhi

Stack optimization for High Speed Networks

Abstract: The growing demand for high-speed networks in domains such as AI data processing, cloud computing, and data centers has amplified the need for optimized software stacks. Traditional network stacks often struggle to meet low-latency and high-throughput requirements. This lecture explores design principles and optimization strategies for achieving efficient data flow across network layers. Key focus areas include protocol tuning, zero-copy mechanisms, hardware offloading, and concurrency management. By addressing these bottlenecks, students will gain insight into how system-level optimization directly influences end-to-end network performance in next-generation communication infrastructures.

Bibhay Ranjan

Senior System Software Engineer, Nvidia Bengaluru India