IEEE-iSES

Biography of tutorial speakers:

Sneh Saurabh obtained his Ph.D. from IIT Delhi in 2012 and B.Tech. (EE) from IIT Kharagpur in the year 2000. He has rich experience in the semiconductor industry, having spent 16 years working for industry leaders such as Cadence Design Systems, Synopsys India, and Magma Design Automation. He has been involved in developing some of the well-established industry-standard EDA tools for clock synchronization, constraints management, STA, formal verification, and physical design. He has been teaching semiconductor-specific courses since 2016 at IIIT Delhi. His teaching has been rated excellent by students consistently, and he has received the Teaching Excellence award for seven consecutive semesters at IIITD. His current research interests are in the areas of VLSI Design and Automation, Energy-Efficient Systems, and Stochastic Computational Frameworks. He is the author of the books “Introduction to VLSI Design Flow” and “Fundamentals of Tunnel Field-Effect Transistors” and holds three US patents. He is an Editor (IETE Technical Review), an Associate Editor (IEEE Access), a Review Editor (Frontiers in Electronics Integrated Circuits and VLSI), and a Senior Member of IEEE.

Biography of tutorial speakers:

Virendra Singh is currently a professor of Electrical and Computer Science at IIT Bombay. He received the B.E. and M.E. degrees in electronics and communication engineering from the Malaviya National Institute of Technology (MNIT), Jaipur, India, in 1994 and 1996, respectively, and the Ph.D. degree in computer science and engineering from the Nara Institute of Science and Technology (NAIST), Nara, Japan, in 2005.

Prior to joining IIT Bombay, he was a Faculty Member at the Supercomputer Education and Research Centre (SERC), Indian Institute of Science (IISc), Bengaluru, India, from 2007 to 2011. His research interests include high-performance computer architecture, testing and verification of high-performance processors, fault-tolerant computing, VLSI testing, design for test, formal verification of hardware designs, embedded system design, design for reliability, and CAD of VLSI Systems.

His research interests are in Cyber security, cyber physical systems, computer architecture, formal methods, VLSI testing and verification, Reinforcement Learning, adversarial learning, security of AI-based systems, blockchain technology, and hybrid quantum-HPC systems. He is an adjunct professor at various IITs and NITs. The following are various roles he is associated with-

Research Lab.: Computer Architecture and Dependable Systems Lab. (CADSL)
Coordinator: Indo-Japanese Joint Laboratory for Intelligent Dependable Cyber Physical Systems (IDCPS)
Coordinator: Information Security Research and Development Centre (ISRDC)
Associated Lab: Centre of excellence for Blockchain research
Affiliation: Centre for Machine Intelligence and Data Science

Biography of tutorial speakers:

He is continuously seeking technical growth and its applications. He currently works at Nvidia India in the areas of Wifi and GPS software development for Android OS, Android wifi stack (sniffer capture, 802.11 protocol, firmware (closed source from vendor), driver, network kernel stack, wpa_supplicant, frameworks, android app) debugging and development..

Biography of tutorial speakers:

Leading the Big Data Analytics (BDA) Lab and the Software Engineering Research Lab (SERL) at IIITA, I am focused on advancing Software Engineering for AI (SE4AI) and AI for Software Engineering (AI4SE). My skill set includes hands-on experience with high-performance computing platforms like Apache Spark and Apache Flink.

Her scholarly work includes over 150 publications, and she has contributed significantly to international conferences and research collaborations in many Europeans and Asian countries. She has chaired conferences such as ISEC 2023, CONIP 2022, BDA 2021 and MISP 2019 and initiated the Core Data Science workshop series. As a PI and Project Manager of ERASMUS TEAL 2.O at IIITA and an active member of IEEE and ACM, her global outreach and editorial contributions to SCI-indexed journals reflect her commitment to academia. Mentoring is a vital aspect of her role, guiding nine Ph.D. scholars and numerous UG/PG students, focusing on their growth in data analytics and machine learning.

Biography of tutorial speakers:

Jatin Chakravarti: He is currently working as a DFT Senior Engineer (L1) at eInfochips (An Arrow Company), Ahmedabad.

His technical skills include RTL Testability Analysis, Scan Insertion, Compression, MBIST, Synthesis, ATPG, Block/Top level simulations (Timing: SDF), Pattern Retargeting. He has experience working on CAD tools like TestMAX Advisor (Spyglass), Design Compiler, DFTMAX, TetraMAX, Fusion Compiler, Formality, Tessent TestKompress, VCS, Verdi, QuestaSim.

Chintan Panchal: He is currently a Fellow at eInfochips, with 23 years of experience in the VLSI- Semiconductor/ASIC industry.

He has full ASIC development cycle experience in RTL Design, DV-Verification, DFT across technologies from 3nm to 28nm for consumer, networking, processor, IPs, and server applications. His expertise includes defining project schedules, manpower estimates, DFT planning and implementation, TVG, test vector validation, IP DFT insertion, silicon bring-up support, failure diagnosis, and yield analysis. He has also worked extensively on verification environments for ASIC and ARM-based SoCs, successfully executing multimillion-gate projects both onsite and offshore.