15-17 December 2025, Jaipur, India
AVP CCS HW Engineering, Marvell India Bengaluru
Title awaited
Gaurav Jalan has more than two decades of extensive industry experience with successful stints as Executive, Manager, Individual contributor & Entrepreneur. With the belief that 'people' are the biggest asset, he enjoy working with individuals & teams to channelize the energy in reaching their true potential. 'Collaboration' is another aspect that I strongly advocate to nurture 'growth mindset' - Together, we can! He likes pursuing challenges head-on & leads the change, whether Technical or Cultural. He has built & led high-performing teams for Product Engineering solutions successfully. Delivered programs in a variety of domains covering Custom silicon, DPU, AI, Servers, Automotive, Networking, Wearables, Mobile, Storage, Connectivity & Graphics. Lead multiple SoCs, ASICs & Test chips with first silicon success. Expert in development & packaging of IP/VIP as an offering. Actively participates in early customer engagement, tailoring custom solutions, specification to end product development with excellence in execution. Proficient in collaborating with multi-site & multi-function teams globally
Well connected & a recognized leader in the Indian ecosystem. Actively participate in programs initiated by the government related to skill development & startup awareness. Other notable contributions include DVCon India, VLSID conference, widely read blogger, invited speaker and panelist to various industry forums.
Director of Engineering Qualcomm India
Multiphase in system BIST for automotive design
Rajesh Kumar Tiwari is the Director of Engineering at Qualcomm India Private Ltd, Bangalore, bringing over 21 years of experience in the VLSI industry, including more than 11 years at Qualcomm. He leads the development and deployment of DFT Scan Architecture and InSystem BIST solutions across Mobile, Compute, and Automotive products. Before joining Qualcomm, Rajesh spent a decade at Texas Instruments, where he architected DFT strategies for highly complex SoC designs. He holds a Master’s degree in VLSI from MNIT Jaipur, India, and is a recognized innovator with multiple patents. Rajesh is also an active contributor to the IEEE, particularly in the domain of Semiconductor Test and DFT.
Chief Scientist at CSIR-CEERI, Pilani, Semiconductor Sensors and Microsystem Group
Wide and Ultra wide bandgap semiconductors for Electric Vehicle
Dr.-Ing. Nidhi Chaturvedi is Sr. Principal Scientist at CSIR-Central Electronics Engineering Research Institute, Pilani, Rajasthan, India. She is also Professor at Academy of Scientific and Innovative Research (AcSIR), Ghaziabad, Uttar Pradesh, India. As an additional role, she had been the Technology and IP In-charge of CSIR-CEERI for about 5 years.
She received her Master degree in Electronics from Banasthali Vidyapith, Rajasthan, India, and the Ph.D. (Dr.-Ing.) from the Technical University, Berlin, Germany. She worked as a Gallium Nitride Device Researcher at FBH, a Leibniz-Institute in Berlin, Germany for around 9.5 years. She has been working with CSIR-CEERI, Pilani for around 12 years. Her main research interest and expertise is in the area of Compound Semiconductors (III-V and III-N) device engineering, simulations, design, fabrication, and characterization. Since last 24 years, she is working on the design and fabrication of Gallium Arsenide, Gallium Nitride, and Gallium Oxide based FETs/HEMTs discrete and MMICs for High power, High voltage, Sensing and Biosensing applications. She has about 60 research publications in reputed conferences and journals and 3-book chapters to her credit. She has also guided over 30 B.Tech, M.Tech and Ph.D. students for their thesis. She has reviewed several papers, projects, organized and chaired technical events, and conferences.
She has been involved in the successful execution of various International/National projects and collaborations with European Space Agency-Netherland, Lucent Technologies-Germany, BMBF-Germany, Infineon Technologies-Germany and Austria, Thales-France, Tesat Spacecom-Germany, Nanowave Technologies-Canada, UMS-Germany, QinetiQ-UK, IOP Czech republic, ISRO-SAC-India, MIT Delhi and CSIR-India. List of awards received by her includes Best GaAS 2002 paper award, Milano, Italy; Best CS MANTECH 2011 paper award, USA; Arvind prem smriti award, India-2000,-young scholar of year; HRD Scholarship award_1990, DOE, Govt of India, Gold medallist-98 University award, Awarded by then Prime minister Dr. Manmohan Singh.
Her work is used for sensing, biosensing, and Monolithic Microwave Integrated Circuits (MMICs).
Chief Technology Officer (CTO) - Data Fusion, Internet of Things (IoT) and Artificial Intelligence, Singapore
Title awaited-
Engineering leader with 18+ years of global executive experience in Internet of Things (IoT), Cloud computing, M2M, Big Data, Analytics, Visual Computing, Automotive Telematics, Enterprise IT, Smartcities. Focus on Strategy, Innovation, New business development/ Expansion, Commercial strategies, Presales, Thought leadership, Joint ventures and Public private partnership (PPP). Built Startup ventures, successful IoT operation, IoT platforms, IoT products from scratch. Leadership roles in global IoT, Cloud, IT/ITES, ICT industries and R&D centers. Serve as chief ICT architect and chief instrumentation expert for ICT driven future (smart) cities and on not-for-profit boards.
Nirupam is an expert in the IoT space, leading successive generations of remote connectivity platforms and solutions, playing key roles in designing, evangelizing, and realizing innovative connected product solutions, successful deployment of connected products in the marketplace.
Nirupam provided technical leadership and direction for Device management platforms, Cloud services, cloud CRM, UI/UX-Apps. Leading all aspect of IoT technology R&D, Strategy, Innovation, product management.
Nirupam is also a successful entrepreneur, pioneer in both battery free & battery powered wireless sensing technology solutions, Internet of things (IoT) platform & Analytics engines, with his leadership spinoff two deep tech companies in IoT, Data science, AI & Connected vehicles domain, raised the multi-mli $ fund from Singapore NRF and Private VC’s.
IBM Research India
Title awaited-
Practitioner and leader with 18+ years of experience in Edtech, proven record of driving innovation and disruption in the Education sector through technology. I am part of the Innovation Centre for Education team at IBM India. Passionate about learning and sharing knowledge, I have deep expertise in designing, implementing, and scaling national-level skills building, educational, and training programs for the future workforce.
His work area includes Academic Program Management, Cloud Pre-sales, Cloud Application Development, Electronic Content Management, Competency Development, Mentoring Startups, Curriculum Design, and Project Management. While setting across a few milestones and receiving accolades, in my different roles at IBM, I have worked across many technologies, including Generative AI, Cloud, Blockchain, Internet of Things, Data Science, DevOps, IBM Watson, and contributed to Ecosystem development with stakeholders from ISVs, Startups, and Academia.
He represents IBM in various forums as a technical expert /panelist on various technology areas,
an advisor to a few incubation centers and startups, and an expert on curriculum design and part
of many Academic councils/Board of Studies at various academic bodies/universities, including
AICTE, NITTTR, and many more. He mentors an online community on Blockchain and Cloud, supporting
sessions on IBM Blockchain/Hyperledger and IBM Cloud.
https://www.meetup.com/Exploring-Blockchain-Bangalore-Meetup/
https://www.meetup.com/Bangalore-Softlayer-Meetup/
AVP MBE Software, Marvell Bengaluru
Title awaited-
Leader with expertise in 5GNR, LTE Access network, Cloud Hardware Security Module & Fibre Channel. Good understanding of software and hardware aspects of Wireless, Security & Storage products. Broad range of architecture and design expertise that covers embedded software, application software, reliability, stability & performance aspects of a product in addition to functional aspects.
System Architect with strong technical, knowledge management, field debugging, project management and people management skills. Proven track record with high quality and on time deliverables as per commitments.
Currently leading Marvell's Wireless, Security & Storage Fibre Channel Product Teams. Formerly, Head for Nokia 2G/3G/4G activities (R&D, Technical Support, Professional Services) in HCL Technologies. This was a multi-site organization of 600+ team members across India, China, Mexico, Portugal and USA.
Principal Engineering Manager, Qualcomm, India
Sustainable Architectures and Specialized Chips for Generative AI Workloads.
Generative AI is reshaping how systems are designed, deployed, and experienced, but current computing platforms are straining under its unique demands for massive parallelism, memory bandwidth, and efficiency at scale. This keynote explores emerging architectures and specialized chips purpose-built for generative workloads, spanning foundation model training, low-latency inference, and on-device personalization. It will examine trends such as heterogeneous accelerators, advanced memory hierarchies, chiplet-based designs, and domain-specific instructions that close the gap between model mathematics and silicon, while also addressing energy efficiency, cost, and deployment constraints across cloud and edge environments. By contrasting general-purpose CPUs and GPUs with domain-specific accelerators, the session will unpack where traditional architectures break down and how new design philosophies are redefining performance-per-watt and total cost of ownership for large-scale AI systems.
Drawing on real-world deployment learnings from hyperscale data centers, enterprise clusters, and edge devices, the talk will highlight key design trade-offs, system bottlenecks that still limit generative AI, and patterns of failure and success in scaling models and infrastructure together. Particular emphasis will be placed on hardware–software co-design across algorithms, compilers, runtimes, and interconnects, showing how joint optimization can unlock step-function gains that are not achievable by treating these layers in isolation. Attendees will gain a roadmap of where generative AI hardware is headed over the next 3–5 years—covering process technology, interconnect, packaging, and system architecture—and walk away with actionable insights for architects, system designers, and product leaders who must balance ambition, reliability, and sustainability in this rapidly evolving landscape.
Rohit Gupta is a seasoned semiconductor architect and technology leader whose work spans the entire spectrum of IP and SoC architecture—from concept to tape-out—with a proven record of first-silicon success. As Principal Engineering Manager at Qualcomm, Rohit leads a high-performing team developing low-power management controllers and high-speed hardware acceleration IPs that power Snapdragon platforms across mobile, automotive, compute, IoT, and XR/VR segments.
His technical expertise include ground-up PCI-Express IP architecture and design, video interface IPs such as HDMI and eDP, and RISC microprocessor-based DMA engines. Currently, Rohit is spearheading a cross-disciplinary initiative to apply Generative AI to IP and SoC design workflows, driving innovation while enhancing quality and productivity. Prior to Qualcomm, he held key roles at Mentor Graphics and STMicroelectronics, leading development of strategic IP solutions.
Beyond product execution, Rohit is an active contributor to the PCI-SIG consortium, shaping future PCI-Express specifications. His impact is reflected in multiple U.S. patents and industry awards recognizing his innovations in hardware architecture and semiconductor design.
Rohit earned his B.Tech. in Electronics and Communication Engineering from Malaviya National Institute of Technology (MNIT), Jaipur in 2006. At IEEE ISES 2025, he brings a practitioner’s perspective on designing scalable, power-efficient high-performance AI hardware that is also profitable, and environmentally responsible—paving the way for the sustainable AI era.
Vice President - SoC Engineering Hrdwyr, Bengaluru
Title awaited-
A driven leader with a demonstrated history of delivering successful products. Developed SoCs
for Wireless, Networking, and Storage markets with end-to-end ownership from concept to
qualification phase.
Built, managed, and energized high-performance teams with a culture of innovation.
Strong project management skills, including risk identification, mitigation, and schedule
forecasting.
Passionate change agent striving for enhanced quality, efficiency, and competence in the
organization.
Highly technical professional with business acumen. Nurtured and bolstered business
relationships with customers, resulting in revenue growth.